// ******************************************************************************
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  hva_peh_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// History       :  xxx 2021/04/08 19:34:52 Create file
// ******************************************************************************

#ifndef HVA_PEH_REG_OFFSET_H
#define HVA_PEH_REG_OFFSET_H

/* PEH_PF_REGS Base address of Module's Register */
#define CSR_PEH_PF_REGS_BASE (0x43FF000)

/* **************************************************************************** */
/*                      PEH_PF_REGS Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_PEH_PF_REGS_PCIHDR_ID_REG \
    (CSR_PEH_PF_REGS_BASE + 0x0) /* This register specify the register of config space. */
#define CSR_PEH_PF_REGS_PCIHDR_CMDSTS_REG \
    (CSR_PEH_PF_REGS_BASE + 0x4) /* This register specify the register of config space. */
#define CSR_PEH_PF_REGS_PCIHDR_CLSREV_REG \
    (CSR_PEH_PF_REGS_BASE + 0x8) /* This register specify the register of config space. */
#define CSR_PEH_PF_REGS_PCIHDR_MISC_REG \
    (CSR_PEH_PF_REGS_BASE + 0xC) /* This register specify the register of config space. */
#define CSR_PEH_PF_REGS_PCIHDR_BAR0_REG \
    (CSR_PEH_PF_REGS_BASE + 0x10) /* This register specify the base address register of config space. */
#define CSR_PEH_PF_REGS_PCIHDR_BAR1_REG \
    (CSR_PEH_PF_REGS_BASE + 0x14) /* This register specify the base address register of config space. */
#define CSR_PEH_PF_REGS_PCIHDR_BAR2_REG \
    (CSR_PEH_PF_REGS_BASE + 0x18) /* This register specify the base address register of config space. */
#define CSR_PEH_PF_REGS_PCIHDR_BAR3_REG \
    (CSR_PEH_PF_REGS_BASE + 0x1C) /* This register specify the base address register of config space. */
#define CSR_PEH_PF_REGS_PCIHDR_BAR4_REG \
    (CSR_PEH_PF_REGS_BASE + 0x20) /* This register specify the base address register of config space. */
#define CSR_PEH_PF_REGS_PCIHDR_BAR5_REG \
    (CSR_PEH_PF_REGS_BASE + 0x24) /* This register specify the base address register of config space. */
#define CSR_PEH_PF_REGS_PCIHDR_CBUS_PTR_REG \
    (CSR_PEH_PF_REGS_BASE + 0x28) /* This register specify the base address register of config space. */
#define CSR_PEH_PF_REGS_PCIHDR_SUBSYS_REG \
    (CSR_PEH_PF_REGS_BASE + 0x2C) /* This register specify the base address register of config space. */
#define CSR_PEH_PF_REGS_PCIHDR_EXPRWM_REG \
    (CSR_PEH_PF_REGS_BASE + 0x30) /* This register specify the base address register of config space. */
#define CSR_PEH_PF_REGS_PCIHDR_CAPPTR_REG \
    (CSR_PEH_PF_REGS_BASE + 0x34) /* This register specify the base address register of config space. */
#define CSR_PEH_PF_REGS_PCI_RSVD_REG (CSR_PEH_PF_REGS_BASE + 0x38) /* reserved */
#define CSR_PEH_PF_REGS_PCIHDR_INT_REG \
    (CSR_PEH_PF_REGS_BASE + 0x3C) /* This register specify the base address register of config space. */
#define CSR_PEH_PF_REGS_PCIE_CAPABILITY_HEADER_REG \
    (CSR_PEH_PF_REGS_BASE + 0x40) /* This is the pcie capability header register */
#define CSR_PEH_PF_REGS_DEVICE_CAPBILITY_REG \
    (CSR_PEH_PF_REGS_BASE + 0x44) /* This register describe the device capability */
#define CSR_PEH_PF_REGS_DEVICE_CTRL_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x48) /* device control status register */
#define CSR_PEH_PF_REGS_LINK_CAPBILITY_REG (CSR_PEH_PF_REGS_BASE + 0x4C)     /* Link capability register */
#define CSR_PEH_PF_REGS_LINK_CTRL_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x50)   /* Link control register */
#define CSR_PEH_PF_REGS_SLOT_CAPABILITY_REG (CSR_PEH_PF_REGS_BASE + 0x54)    /* Slot capability register */
#define CSR_PEH_PF_REGS_SLOT_CTRL_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x58)   /* Slot control and status register */
#define CSR_PEH_PF_REGS_ROOT_CTRL_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x5C)   /* Root control status */
#define CSR_PEH_PF_REGS_ROOT_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x60)        /* Root status register */
#define CSR_PEH_PF_REGS_DEVICE_CAPABILITY2_REG (CSR_PEH_PF_REGS_BASE + 0x64) /* device capability 2 register */
#define CSR_PEH_PF_REGS_DEVICE_CTRL2_REG (CSR_PEH_PF_REGS_BASE + 0x68)       /* Device control register 2 */
#define CSR_PEH_PF_REGS_LINK_CAPABILITY2_REG (CSR_PEH_PF_REGS_BASE + 0x6C)   /* Link capability 2 */
#define CSR_PEH_PF_REGS_LINK_CTRL_STATUS2_REG (CSR_PEH_PF_REGS_BASE + 0x70)  /* Link control and status 2 */
#define CSR_PEH_PF_REGS_SLOT_CAP_2_REG (CSR_PEH_PF_REGS_BASE + 0x74)         /* Slot Capabilities 2 Register */
#define CSR_PEH_PF_REGS_SLOT_CTRL_2_REG (CSR_PEH_PF_REGS_BASE + 0x78)        /* Slot Control 2 Register */
#define CSR_PEH_PF_REGS_MSI_CAP_HEADER_REG \
    (CSR_PEH_PF_REGS_BASE + 0x80) /* MSI Capability Header and   Message Control register */
#define CSR_PEH_PF_REGS_MSI_ADDR_REG (CSR_PEH_PF_REGS_BASE + 0x84)    /* Message Address Register for MSI */
#define CSR_PEH_PF_REGS_MSI_UP_ADDR_REG (CSR_PEH_PF_REGS_BASE + 0x88) /* Message Upper Address Register for MSI */
#define CSR_PEH_PF_REGS_MSI_DATA_REG (CSR_PEH_PF_REGS_BASE + 0x8C)    /* Message Data Register for MSI */
#define CSR_PEH_PF_REGS_MSI_MASK_REG (CSR_PEH_PF_REGS_BASE + 0x90)    /* Mask Bits Register for MSI */
#define CSR_PEH_PF_REGS_MSI_PENDING_REG (CSR_PEH_PF_REGS_BASE + 0x94) /* Pending Bits Register for MSI */
#define CSR_PEH_PF_REGS_MSIX_CAP_HEADER_REG \
    (CSR_PEH_PF_REGS_BASE + 0xA0) /* MSI-X Capability Header and   Message Control register */
#define CSR_PEH_PF_REGS_MSIX_TABLE_REG (CSR_PEH_PF_REGS_BASE + 0xA4)     /* Table Offset/Table BIR Register for MSI-X */
#define CSR_PEH_PF_REGS_MSIX_PBA_REG (CSR_PEH_PF_REGS_BASE + 0xA8)       /* PBA Offset/PBA BIR Register for MSI-X */
#define CSR_PEH_PF_REGS_PME_CAP_HEADER_REG (CSR_PEH_PF_REGS_BASE + 0xB0) /* PME capability header and PME control */
#define CSR_PEH_PF_REGS_PME_CTRL_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0xB4) /* Power management status register */
#define CSR_PEH_PF_REGS_ACS_EXTENDED_CAP_HEADER_REG (CSR_PEH_PF_REGS_BASE + 0x100) /* ACS Extended capability header \
                                                                                    */
#define CSR_PEH_PF_REGS_ACS_CTRL_REG (CSR_PEH_PF_REGS_BASE + 0x104)                /* ACS Control Register */
#define CSR_PEH_PF_REGS_SRIOV_CAP_HEADER_REG (CSR_PEH_PF_REGS_BASE + 0x200)        /* SRIOV capability header */
#define CSR_PEH_PF_REGS_SRIOV_CAP_REG (CSR_PEH_PF_REGS_BASE + 0x204)               /* SRIOV capability */
#define CSR_PEH_PF_REGS_SRIOV_CTRL_REG (CSR_PEH_PF_REGS_BASE + 0x208)              /* SRIOV control register */
#define CSR_PEH_PF_REGS_INIT_VF_NUMBER_REG (CSR_PEH_PF_REGS_BASE + 0x20C)          /* Initial VF and Totla VF */
#define CSR_PEH_PF_REGS_FUNC_DEP_VF_NUM_REG (CSR_PEH_PF_REGS_BASE + 0x210)  /* Function dependency link and VF NUMBER \
                                                                             */
#define CSR_PEH_PF_REGS_VF_RID_SETTING_REG (CSR_PEH_PF_REGS_BASE + 0x214)   /* First offset and Stride register */
#define CSR_PEH_PF_REGS_VF_DEVICE_ID_REG (CSR_PEH_PF_REGS_BASE + 0x218)     /* VF device ID */
#define CSR_PEH_PF_REGS_VF_PAGE_SIZE_REG (CSR_PEH_PF_REGS_BASE + 0x21C)     /* supported Page Size */
#define CSR_PEH_PF_REGS_SYSTEM_PAGE_SIZE_REG (CSR_PEH_PF_REGS_BASE + 0x220) /* System page size */
#define CSR_PEH_PF_REGS_VF_BAR0_REG (CSR_PEH_PF_REGS_BASE + 0x224) /* Virtual function  Base address 0  register */
#define CSR_PEH_PF_REGS_VF_BAR1_REG (CSR_PEH_PF_REGS_BASE + 0x228) /* Virtual function  Base address 1 register */
#define CSR_PEH_PF_REGS_VF_BAR2_REG (CSR_PEH_PF_REGS_BASE + 0x22C) /* Virtual function  Base address 2 register */
#define CSR_PEH_PF_REGS_VF_BAR3_REG (CSR_PEH_PF_REGS_BASE + 0x230) /* Virtual function  Base address 3 register */
#define CSR_PEH_PF_REGS_VF_BAR4_REG (CSR_PEH_PF_REGS_BASE + 0x234) /* Virtual function  Base address 4 register */
#define CSR_PEH_PF_REGS_VF_BAR5_REG (CSR_PEH_PF_REGS_BASE + 0x238) /* Virtual function  Base address 5 register */
#define CSR_PEH_PF_REGS_VF_MIG_STATE_ARRAY_REG (CSR_PEH_PF_REGS_BASE + 0x23C) /* VF Migration state array offset */
#define CSR_PEH_PF_REGS_TPH_EXTENDED_CAP_HEADER_REG \
    (CSR_PEH_PF_REGS_BASE + 0x300)                                  /* TPH Requester Extended Capability Header */
#define CSR_PEH_PF_REGS_TPH_CTRL_REG (CSR_PEH_PF_REGS_BASE + 0x304) /* TPH Requester Capability Register */
#define CSR_PEH_PF_REGS_TPH_EGRESS_CTRL0_REG (CSR_PEH_PF_REGS_BASE + 0x308) /* TPH Requester Control Register */
#define CSR_PEH_PF_REGS_PASID_EXTENDED_CAP_HEADER_REG \
    (CSR_PEH_PF_REGS_BASE + 0x320)                                    /* PASID Requester Extended Capability Header */
#define CSR_PEH_PF_REGS_PASID_CTRL_REG (CSR_PEH_PF_REGS_BASE + 0x324) /* PASID Requester Capability Register */
#define CSR_PEH_PF_REGS_AER_CAP_HEADER_REG (CSR_PEH_PF_REGS_BASE + 0x400)  /* Advance Error Report capability header */
#define CSR_PEH_PF_REGS_UNCR_ERR_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x404) /* uncorrectable error status */
#define CSR_PEH_PF_REGS_UNCR_ERR_MASK_REG (CSR_PEH_PF_REGS_BASE + 0x408)   /* uncorrectable error mask */
#define CSR_PEH_PF_REGS_UNCR_ERR_SEVERITY_REG (CSR_PEH_PF_REGS_BASE + 0x40C) /* uncorrectable error serverity */
#define CSR_PEH_PF_REGS_COR_ERR_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x410)    /* Correctable error status */
#define CSR_PEH_PF_REGS_COR_ERR_MASK_REG (CSR_PEH_PF_REGS_BASE + 0x414)      /* correctable error mask */
#define CSR_PEH_PF_REGS_ADVACD_CAP_CTRL_REG \
    (CSR_PEH_PF_REGS_BASE + 0x418) /* advanced error capabilities and control register */
#define CSR_PEH_PF_REGS_FIRST_HEADER_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x41C)   /* First DW header log */
#define CSR_PEH_PF_REGS_SECOND_HEADER_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x420)  /* Second DW header log */
#define CSR_PEH_PF_REGS_THIRD_HEADER_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x424)   /* Third DW header log */
#define CSR_PEH_PF_REGS_FOUR_HEADER_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x428)    /* Forth DW header log */
#define CSR_PEH_PF_REGS_RWOT_ERRWR_COMMAND_REG (CSR_PEH_PF_REGS_BASE + 0x42C) /* Root error report command */
#define CSR_PEH_PF_REGS_RWOT_ERRWR_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x430)  /* Roor Error status */
#define CSR_PEH_PF_REGS_ERR_SOURCE_IDEN_REG (CSR_PEH_PF_REGS_BASE + 0x434)    /* Erorr soure identification register */
#define CSR_PEH_PF_REGS_FIRST_PREFIX_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x438)   /* First DW prefix log */
#define CSR_PEH_PF_REGS_SECOND_PREFIX_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x43C)  /* Second DW prefix log */
#define CSR_PEH_PF_REGS_THIRD_PREFIX_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x440)   /* Third DW prefix log */
#define CSR_PEH_PF_REGS_FOUR_PREFIX_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x444)    /* Forth DW prefix log */
#define CSR_PEH_PF_REGS_ARI_CAP_HEADER_REG (CSR_PEH_PF_REGS_BASE + 0x450)     /* ARI capability header */
#define CSR_PEH_PF_REGS_ARI_CTRL_REG (CSR_PEH_PF_REGS_BASE + 0x454)           /* ARI control and capability */

/* PEH_VF_REGS Base address of Module's Register */
#define CSR_PEH_VF_REGS_BASE (0x0)

/* **************************************************************************** */
/*                      PEH_VF_REGS Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_PEH_VF_REGS_VF_PCIHDR_ID_REG \
    (CSR_PEH_VF_REGS_BASE + 0x0) /* This register specify the register of config space. */
#define CSR_PEH_VF_REGS_VF_PCIHDR_CMDSTS_REG \
    (CSR_PEH_VF_REGS_BASE + 0x4) /* This register specify the register of config space. */
#define CSR_PEH_VF_REGS_VF_PCIHDR_CLSREV_REG \
    (CSR_PEH_VF_REGS_BASE + 0x8) /* This register specify the register of config space. */
#define CSR_PEH_VF_REGS_VF_PCIHDR_MISC_REG \
    (CSR_PEH_VF_REGS_BASE + 0xC) /* This register specify the register of config space. */
#define CSR_PEH_VF_REGS_VF_PCIHDR_BAR0_REG \
    (CSR_PEH_VF_REGS_BASE + 0x10) /* This register specify the base address register of config space. */
#define CSR_PEH_VF_REGS_VF_PCIHDR_BAR1_REG \
    (CSR_PEH_VF_REGS_BASE + 0x14) /* This register specify the base address register of config space. */
#define CSR_PEH_VF_REGS_VF_PCIHDR_BAR2_REG \
    (CSR_PEH_VF_REGS_BASE + 0x18) /* This register specify the base address register of config space. */
#define CSR_PEH_VF_REGS_VF_PCIHDR_BAR3_REG \
    (CSR_PEH_VF_REGS_BASE + 0x1C) /* This register specify the base address register of config space. */
#define CSR_PEH_VF_REGS_VF_PCIHDR_BAR4_REG \
    (CSR_PEH_VF_REGS_BASE + 0x20) /* This register specify the base address register of config space. */
#define CSR_PEH_VF_REGS_VF_PCIHDR_BAR5_REG \
    (CSR_PEH_VF_REGS_BASE + 0x24) /* This register specify the base address register of config space. */
#define CSR_PEH_VF_REGS_VF_PCIHDR_CBUS_PTR_REG \
    (CSR_PEH_VF_REGS_BASE + 0x28) /* This register specify the base address register of config space. */
#define CSR_PEH_VF_REGS_VF_PCIHDR_SUBSYS_REG \
    (CSR_PEH_VF_REGS_BASE + 0x2C) /* This register specify the base address register of config space. */
#define CSR_PEH_VF_REGS_VF_PCIHDR_EXPRWM_REG \
    (CSR_PEH_VF_REGS_BASE + 0x30) /* This register specify the base address register of config space. */
#define CSR_PEH_VF_REGS_VF_PCIHDR_CAPPTR_REG \
    (CSR_PEH_VF_REGS_BASE + 0x34) /* This register specify the base address register of config space. */
#define CSR_PEH_VF_REGS_VF_PCI_RSVD_REG (CSR_PEH_VF_REGS_BASE + 0x38) /* reserved */
#define CSR_PEH_VF_REGS_VF_PCIHDR_INT_REG \
    (CSR_PEH_VF_REGS_BASE + 0x3C) /* This register specify the base address register of config space. */
#define CSR_PEH_VF_REGS_VF_PCIE_CAPABILITY_HEADER_REG \
    (CSR_PEH_VF_REGS_BASE + 0x40) /* This is the pcie capability header register */
#define CSR_PEH_VF_REGS_VF_DEVICE_CAPBILITY_REG \
    (CSR_PEH_VF_REGS_BASE + 0x44) /* This register describe the device capability */
#define CSR_PEH_VF_REGS_VF_DEVICE_CTRL_STATUS_REG (CSR_PEH_VF_REGS_BASE + 0x48) /* device control status register */
#define CSR_PEH_VF_REGS_VF_LINK_CAPBILITY_REG (CSR_PEH_VF_REGS_BASE + 0x4C)     /* Link capability register */
#define CSR_PEH_VF_REGS_VF_LINK_CTRL_STATUS_REG (CSR_PEH_VF_REGS_BASE + 0x50)   /* Link control register */
#define CSR_PEH_VF_REGS_VF_SLOT_CAPABILITY_REG (CSR_PEH_VF_REGS_BASE + 0x54)    /* Slot capability register */
#define CSR_PEH_VF_REGS_VF_SLOT_CTRL_STATUS_REG (CSR_PEH_VF_REGS_BASE + 0x58)   /* Slot control and status register */
#define CSR_PEH_VF_REGS_VF_ROOT_CTRL_STATUS_REG (CSR_PEH_VF_REGS_BASE + 0x5C)   /* Roor control status */
#define CSR_PEH_VF_REGS_VF_ROOT_STATUS_REG (CSR_PEH_VF_REGS_BASE + 0x60)        /* Root status register */
#define CSR_PEH_VF_REGS_VF_DEVICE_CAPABILITY2_REG (CSR_PEH_VF_REGS_BASE + 0x64) /* device capability 2 register */
#define CSR_PEH_VF_REGS_VF_DEVICE_CTRL2_REG (CSR_PEH_VF_REGS_BASE + 0x68)       /* Device control register 2 */
#define CSR_PEH_VF_REGS_VF_LINK_CAPABILITY2_REG (CSR_PEH_VF_REGS_BASE + 0x6C)   /* Link capability 2 */
#define CSR_PEH_VF_REGS_VF_LINK_CTRL_STATUS2_REG (CSR_PEH_VF_REGS_BASE + 0x70)  /* Link control and status 2 */
#define CSR_PEH_VF_REGS_VF_SLOT_CAP_2_REG (CSR_PEH_VF_REGS_BASE + 0x74)         /* Slot Capabilities 2 Register */
#define CSR_PEH_VF_REGS_VF_SLOT_CTRL_2_REG (CSR_PEH_VF_REGS_BASE + 0x78)        /* Slot Control 2 Register */
#define CSR_PEH_VF_REGS_VF_MSI_CAP_HEADER_REG \
    (CSR_PEH_VF_REGS_BASE + 0x80) /* MSI Capability Header and   Message Control register */
#define CSR_PEH_VF_REGS_VF_MSI_ADDR_REG (CSR_PEH_VF_REGS_BASE + 0x84)    /* Message Address Register for MSI */
#define CSR_PEH_VF_REGS_VF_MSI_UP_ADDR_REG (CSR_PEH_VF_REGS_BASE + 0x88) /* Message Upper Address Register for MSI */
#define CSR_PEH_VF_REGS_VF_MSI_DATA_REG (CSR_PEH_VF_REGS_BASE + 0x8C)    /* Message Data Register for MSI */
#define CSR_PEH_VF_REGS_VF_MSI_MASK_REG (CSR_PEH_VF_REGS_BASE + 0x90)    /* Mask Bits Register for MSI */
#define CSR_PEH_VF_REGS_VF_MSI_PENDING_REG (CSR_PEH_VF_REGS_BASE + 0x94) /* Pending Bits Register for MSI */
#define CSR_PEH_VF_REGS_VF_MSIX_CAP_HEADER_REG \
    (CSR_PEH_VF_REGS_BASE + 0xA0) /* MSI-X Capability Header and   Message Control register */
#define CSR_PEH_VF_REGS_VF_MSIX_TABLE_REG (CSR_PEH_VF_REGS_BASE + 0xA4) /* Table Offset/Table BIR Register for MSI-X \
                                                                         */
#define CSR_PEH_VF_REGS_VF_MSIX_PBA_REG (CSR_PEH_VF_REGS_BASE + 0xA8)   /* PBA Offset/PBA BIR Register for MSI-X */
#define CSR_PEH_VF_REGS_VF_PME_CAP_HEADER_REG (CSR_PEH_VF_REGS_BASE + 0xB0)  /* PME capability header and PME control \
                                                                              */
#define CSR_PEH_VF_REGS_VF_PME_CTRL_STATUS_REG (CSR_PEH_VF_REGS_BASE + 0xB4) /* Power management status register */
#define CSR_PEH_VF_REGS_VF_ACS_EXTENDED_CAP_HEADER_REG \
    (CSR_PEH_VF_REGS_BASE + 0x100)                                     /* ACS Extended capability header */
#define CSR_PEH_VF_REGS_VF_ACS_CTRL_REG (CSR_PEH_VF_REGS_BASE + 0x104) /* ACS Control Register */
#define CSR_PEH_VF_REGS_VF_TPH_EXTENDED_CAP_HEADER_REG \
    (CSR_PEH_VF_REGS_BASE + 0x300)                                     /* TPH Requester Extended Capability Header */
#define CSR_PEH_VF_REGS_VF_TPH_CTRL_REG (CSR_PEH_VF_REGS_BASE + 0x304) /* TPH Requester Capability Register */
#define CSR_PEH_VF_REGS_VF_TPH_EGRESS_CTRL0_REG (CSR_PEH_VF_REGS_BASE + 0x308) /* TPH Requester Control Register */
#define CSR_PEH_VF_REGS_VF_ARI_CAP_HEADER_REG (CSR_PEH_VF_REGS_BASE + 0x450)   /* ARI capability header */
#define CSR_PEH_VF_REGS_VF_ARI_CTRL_REG (CSR_PEH_VF_REGS_BASE + 0x454)         /* ARI control and capability */

#endif // HVA_PEH_REG_OFFSET_H
